It’s been a while since we’ve seen a brand new microprocessor company, but recently, Silicon Valley startup Soft Machines has announced a new processor architecture called VISC (which -for the record- doesn’t stand for anything).

Before we dive into the technical details, a bit about Soft Machines itself. The company is already seven years old, has 250 employees, has been working on nothing but this project and has already raised $125 million in venture capital. Among its investors we find big names like Samsung Ventures, AMD and Mubadala. So far, so credible.

But what exactly is this new CPU architecture? Which problems does it promise to solve, and how is it planning to do this?

A different approach towards single-threaded programs

Although multi-core processors are todays standard, they often don’t bring you the expected performance gain linked to an extra pair of cores. Mostly this is due to the programs. To benefit from a multicore architecture, you need parallelized programs, which are broken into separate threads that can execute independently. Writing such programs is easier said than done.

Most of the time, programmers just don’t write multi-threaded programs.

What you often see when running single threaded applications on a multicore CPU is that for the most part, only one core is doing the job, while the others are just being idle. The ultimate scenario would be to run single-threaded programs on a multicore architecture while using the power of all cores simultaneously instead of just executing the code on one single core. Until recently, this procedure seemed only to exist in theory, but executing single-threaded code parallelized on multiple cores is exactly what VISC is promising to do. Bottom line: Soft Machines promises a better absolute performance on single-threaded code.

How does it work?

Like others VISC is a multi-core processor, which means it’s got two or more CPU cores running side by side. But where most multicore processor have a one-to-one correlation between threads and cores, VISC has a different approach. In the VISC architecture there’s no one-to-one correlation between threads and cores. One thread might run on both cores, borrowing resources from its neighbouring core. This allows a thread to spread itself across all the resources of the chip in order to execute in the minimum amount of time. The level at which it can borrow resource from neighbouring cores is also very fine-grained. If one thread uses for example one-and-a-half cores, the remaining half-core can execute another thread.


In order to achieve this VISC’s hardware focuses on extracting ILP (instruction-level parallelism) from a workload, then scheduling that workload in very small threads across a certain number of cores.

The mechanism to do this lies part in the CPU core, and part appears earlier in the pipeline, in a feature called the Global Front End (GPE). The GFE fetches code from VISC’s unified instruction cache and starts the process of looking for parallelism and dependencies. It does this largely by a process of elimination, looking for instructions that are interdependent because they use the same registers, depend upon each other’s output, or reference the same pointers.


In a number of benchmark tests, VISC outperformed an ARM Cortex-15 in every category – often by more than 2x or 3x. In the best case, it was nearly 7x faster and the un-weighted average of all the benchmarks was around 3x ARM’s average performance.

Some could argue the fact that these benchmarks were run by Soft Machines makes these results biased, but since they include such reliable benchmarks as SPECint, SPECfp and EEMBC, it clearly would have been difficult for them to manipulate the outcome.


If you take a closer look, you will notice that all scores are measured in units of performance per MHz and as not absolute performance. VISC might be faster than Cortex-A15 in terms of instructions per clock, but if you’re running your current chip above about 500 MHz, it’s probably faster than VISC.

Soft Machines haven’t said how fast VISC will run, but it seems 500 MHz is a good guess. Compared to 2.5 GHz for ARM’s Cortex-A15 and 4 GHz for Intel’s Core i7, VISC is probably not going to beat these if it comes to absolute performance. Down the road, Soft Machines say an x86 version is in the works, and a VISC native Java version is a possibility, so it’d be interesting to see what this looks like.

Keeping in mind that Soft Machines says a two-core VISC can deliver the same performance as an A15 while using just one-third the power, VISC delivers a better performance-per-watt curve than the  ARM family. In my opinion, it looks like someone has beaten ARM at its own game.


VISC: A New CPU Architecture That Beats ARM At Its Own Game

About The Author
- Gert is the product manager of Parleys and co-hosts the Devoxx Future track


  • Jock Murphy

    So no details about the visc processor, even on the site itself. No details about the benchmark. No idea of the speed of the processor, power consumption, or anything relevant; no details about the ISA, tools support, if the speed gains require any changes to the software itself…

    …And you are prepared to say it “Beats ARM At Its Own Game”. What game is that? Making wild claims? Producing unbuyable CPUs?

  • Stephan Sokolow

    Sounds to me like they’re trying to claim that the Instruction-Level Parallelism that Intel, AMD, and anyone else making competitive processors have been using refining for over a decade is something new and special rather than a hard research problem requiring a lot of trade-secret special-sauce fine-tuning to remain competitive.

    (Look up terms like “Out-of-order execution”, “branch prediction”, “speculative execution”, and “instruction pipelining” on Wikipedia)

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <s> <strike> <strong>